1. Field
This disclosure relates generally to semiconductor die, and more specifically, to a semiconductor die structure with die pad patterns.
2. Related Art
Traditional semiconductor die pad arrays for example such as commonly found on die intended for flip-chip packages, utilize an undesirably large pad pitch which limits the number of pads that can be put on the die surface and utilize patterns which are inefficient for applications requiring a minimum number of layers for pad array escape routing. Pads which are patterned in conventional rectangular, checkerboard or closest-packed arrays are difficult to escape in a package requiring a minimum number of layers because typical package routing technology constraints prevent escape of more than two rows per routing layer and six or more rows are typically used. However, in traditional package substrates and in embedded chips package technologies using buildup-type layering, it would be desirable to be able to use at most only one or two routing layers for escape.
Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.